Detail IC ESMT M12L128168
2M x 16 Bit x 4 Banks
Synchronous DRAM ( SDRAM) JEDEC standard 3.3V power supply The M12L128168A is 134, 217, 728 bits synchronous high data rate Dynamic RAM organized as 4 x 2, 097, 152 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/ O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
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